In order to prevent reduction in the yield of the manufacturing line of microdevices such as semiconductor devices, it is essential to maintain the high overlay accuracy among the layers in overlay exposure in which shot areas are formed by transfer on a substrate such as a wafer (hereinafter, generally referred to as a “wafer”) by overlaying multiple layers of circuit patterns and the like in the lithography process.
In addition, recently, in order to increase the productivity, a lithography system in which a plurality of projection exposure apparatuses are prepared and a host computer extensively controls the projection exposure apparatuses has been set up. In such a system, since circuit patterns of respective layers are transferred on one wafer using different projection exposure apparatuses in order to increase the productivity, the scheduling of the projection exposure apparatuses on the overlay exposure is required. For example, in the case where a projection exposure apparatus that is used for exposure in a previous process layer on a wafer (hereinafter, also simply referred to as a “previous process”) is in operation, the entire exposure process can be shortened by conducting the scheduling so that another projection exposure apparatus that is not in operation at present is used for exposure of a present process layer (a current layer: hereinafter, also simply referred to as a “present process”).
It is the difference in distortion of transferred image among projection exposure apparatuses that becomes a problem when executing such scheduling. In order to prevent electrical connection points of the circuits from relatively being displaced among layers due to the distortion difference among the apparatuses, it is required to secure the overlay accuracy of the images among layers. In order to secure the overlay accuracy of the images among layers, it is important to perform matching of such distortion among the projection exposure apparatuses.
In response to the increased requirement for the higher overlay accuracy in order to cope with the higher integration of semiconductor devices, as a system that performs this type of distortion matching among a plurality of projection exposure apparatuses, a lithography system has recently been proposed that aims at reducing as much as possible the shot shape error among layers caused by the difference of the image distortion correction capability among the apparatuses and/or change over time (e.g. refer to Patent Document 1).
In the lithography system described in Patent Document 1, as a principle, there is only one previous process layer that can be designated with respect to one present process layer, and even in the case where a plurality of previous process layers are designated, only the distortion matching, in which the average of distortion of the projected images in the previous process layers is assumed as a reference, is performed. However, in the actual circuit design, in the most cases, a layer that has a strong link with an electric wire extending in an X-axis direction, which is one of datum axes within a wafer surface, is different from a layer that has a strong link with an electric wire extending in a Y-axis direction in the circuit of the same layer. Accordingly, in such cases, it can be said that it is more desirable from the viewpoint of circuit design to make a distortion component in the X-axis direction conform to a distortion component of a layer that has a strong link with it and to make a distortion component in the Y-axis direction conform to another layer that has a strong link with it than to adjust distortion using the average of distortion of projected images in the previous process layers, and the like.
In order to cope with such cases, a method in which information used for alignment is separately detected for the X-axis and the Y-axis is also proposed, but it is the actual situation in which the specific realization means has not yet been proposed with regard to how to separately perform adjustment with respect to the X-axis and the Y-axis in the case where the overly exposure is performed also taking into consideration distortion of projected images and a nonlinear component of the array of shot areas formed on a wafer W by exposure.    Patent Document 1: Kokai (Japanese Unexamined Patent Application Publication) No. 2000-036451    Patent Document 2: Japanese Patent No. 2591746